In recent years, complementary metal oxide semiconductor (CMOS) image sensors have been widely used as an (solid state) imaging element from the viewpoint of cost and the like.
In the CMOS image sensor, a slope type AD converter is widely used for AD conversion of electric signals (hereinafter also referred to as “pixel signals”) output from pixels. In the slope type AD converter, AD conversion of the pixel signal is performed by using a ramp waveform as a reference signal (voltage), comparing the reference signal with the pixel signal through a comparator, and counting a period of time until an output of the comparator is inverted through a counter.
Further, the slope type AD converter is excellent in linearity and noise characteristics, and it is possible to configure a column AD converter that simultaneously performs AD conversion on all columns by arranging the slope type AD converter for each pixel column, for example.
According to the column AD converter, it is possible to speed up the AD conversion by lowering an operating frequency per slope type AD converter. Further, in the column AD converter, since a reference signal generating circuit that generates the reference signal can be shared by the slope type AD converters of the respective columns, efficiency of an area and power consumption are high.
Thus, the slope type AD converter is better in compatibility with the CMOS image sensor than other AD conversion types.
Note that a technique of reducing power consumption by configuring a counter with a latch circuit that latches lower bits of a count value of a counter using a gray code and a binary ripple counter that counts upper bits of the count value using a binary code has been proposed in Patent Document 1.
In Patent Document 1, first and second latch methods have been proposed as a latch method of latching the gray code by the latch circuit for the lower bits of the count value.
In the first latch method, the latch circuit is operated from the start of the AD conversion, and the gray code is latched by the latch circuit at a timing at which the output of the comparator is inverted. In the second latch method, the latch circuit is operated at a timing at which the output of the comparator is inverted, and the gray code is latched by the latch circuit at a timing at which a delay signal obtained by delaying the output of the comparator is inverted. Using the second latch method, it is possible to reduce the power consumption to be smaller than in the first latch method.
In Patent Document 1, the upper bits of the count value are counted by the binary counter. The binary counter starts the counting from the start of the AD conversion and stops the counting at a timing at which the output of the comparator is inverted.